SiFive Launches CPU IP Industry into the Cloud with New RISC-V Cores and an Easy Online Business Model

SAN FRANCISCO – May 4, 2017 – SiFive, the company founded by the inventors of the free and open RISC-V instruction set architecture (ISA), today announced the immediate availability of its Coreplex IP, the fastest and easiest way to license RISC-V cores. With the rapid growth in the RISC-V ecosystem, SiFive Coreplex IP designs have become the de facto leader for RISC-V cores, with more public customers, silicon and development boards than any other RISC-V vendor. SiFive’s hassle-free “study-evaluate-buy” purchase process means that designers can get their hands on Coreplex IP RTL in a matter of minutes.

“As an engineer, trying to get information from your average IP vendor is an exercise in futility,” said Yunsup Lee, CTO and co-founder, SiFive. “The countless number of NDAs, partial answers and sales meetings you must agree to just to get basic evaluation material makes it feel like they don’t want your business. It’s unbelievable how far behind the industry is compared to the ease in which SaaS companies provide their products. When we founded SiFive, we wanted to change that. Through our ‘study-evaluate-buy’ model, we’ve made Coreplex IP licensing as easy as buying a subscription to any modern software service.”

SiFive’s website has all the information a designer needs to study the IP, including full datasheets, specifications and app notes, all available without an NDA. With one click, the designer can get instant access to full FPGA bitstream models to test software, SDK and tools. Fully functional, synthesizable evaluation RTL is also available instantly, allowing the designer to synthesize and simulate in their own design environment and process nodes. Finally, a simple seven-page contract with transparent pricing makes it straightforward and easy to license the IP for commercial use.

RISC-V Ecosystem

RISC-V has developed a strong ecosystem comprising over 60 companies including Google, HPE, Microsoft, IBM, Qualcomm, NVIDIA, Samsung and Microsemi to name a few. Member companies as well as third-party open-source contributors are actively contributing to a maturing stable of software and toolchains, including GCC and binutils, both of which have been upstreamed. SiFive maintains an easy to install toolchain, SDK and BSPs with binaries of the latest open source tools, including OpenOCD, GNU Debugger, Arduino IDE, and the Eclipse integrated development environment. More updates are expected at the 6th RISC-V Workshop, May 8-11 in Shanghai.

SiFive Coreplex IP

SiFive Coreplex IP is silicon proven and developed by the inventors of the RISC-V ISA. Built on years of research and continuous refinement throughout multiple tapeouts, SiFive’s Coreplex IP has demonstrated significantly better power efficiency compared to other, competing ISAs. Two initial Coreplex design configurations are available at launch:

• E31 Coreplex – The most deployed RISC-V core in the world, the E31 Coreplex is designed for low power, high performance, 32-bit embedded applications such as Edge Computing, Smart IoT or Wearables.
• E51 Coreplex – A 64-bit embedded core, the E51 Coreplex is the ideal solution to act as a system or host control core inside larger 64-bit SoCs, as its small size and performance efficiency set it apart from the typical, bloated and large 64-bit processors while still maintaining full software compatibility with mainstream toolchains.

Coreplex Ecosystem

SiFive has partnered with multiple companies that are making the Coreplex IP available to their downstream customers. This development of this expanded distribution network has come as a result of the expanding popularity and demand for RISC-V hardware.

“We’ve collaborated with SiFive to bring its Coreplex IP technology to our IGLOO2 and RTG4 FPGA platform,” said Bruce Weyer, vice president and business unit manager for the SoC Products Group at Microsemi. “Led by the inventors of RISC-V, SiFive brings a huge amount of credibility to the quality of their RISC-V cores when we worked with our downstream customers.”

“SiFive has significantly streamlined the licensing process for RISC-V cores,” said Vicson Liu, executive vice president of United Design Service. “Through Coreplex IP, our customers can now easily evaluate and buy 32-bit and 64-bit RISC-V IP to enable their high-performance chip designs.”

“We have been excited by the growth and demand for RISC-V cores from our customers,” said Flash Lin, Chief Operation Officer at Faraday. “By partnering with SiFive to deliver high performance and proven IP, we can quickly service our customer requirements in this rapidly growing ecosystem.”

Learn more about the Coreplex IP partners.

For more information about the “study-evaluate-buy” path to SiFive’s Coreplex IP, please visit the SiFive Core Designer page.

About SiFive

SiFive is the first fabless semiconductor company to build customized silicon based on the open-source RISC-V instruction set architecture. Founded by RISC-V inventors Yunsup Lee, Andrew Waterman and Krste Asanovic, SiFive is democratizing access to custom silicon and drastically reducing the ease at which system designers and makers alike can get access to licensable IP. SiFive is located in San Francisco and has venture backing from Sutter Hill Ventures. For more information visit www.sifive.com.

MEDIA CONTACTS

Jack Kang
SiFive
(510) 673-1309
jack@sifive.com

Alex Trulio
SHIFT Communications for SiFive
(415) 591-8452
atrulio@shiftcomm.com